The present invention relates to a data transfer device and a data transfer method which are employed when data to be subjected to data processing using an array of a matrix format (rows and columns) are stored in or read from a RAM and, more particularly, to those suitable for the use of a paging RAM in data processing using an array having error correction codes in both the rows and the columns.
When recording or transmitting data, for efficient recording or transmission, data are subjected to compression or coding according to a predetermined method, and the compressed or coded data are subjected to decompression or decoding which is the inverse of compression or coding, to be utilized. Further, in order to check and correct errors in data caused by noise or signal attenuation in reading, writing, or transmission of the data, predetermined codes for error checking and correction (hereinafter referred to as xe2x80x9cerror correcting codesxe2x80x9d) are assigned according to a method such as parity bit, checksum, or cyclic redundancy check (CRC) when recording or transmitting the data, and error checking and correction (hereinafter referred to as xe2x80x9cECCxe2x80x9d) using the error correcting codes is performed when decoding the data, whereby reliability is improved.
For example, there is a method in which data are arranged according to a format for error checking and correction having predetermined rows and columns, and row-direction parity data or column-direction parity data (error detecting codes) are assigned to every row or column.
In arithmetic operation to data such as ECC, a DRAM (Dynamic Random Access Memory), which has widely used in computer systems, is employed as a temporary storage means for working storage. A DRAM has addresses in both the row direction and the column direction, and data storage positions in the DRAM are specified by addressing. So, it is possible to realize a storage state suited to a format for error checking and correction, by successively storing data in the DRAM while specifying the storage positions.
Further, a paging DRAM in which data are processed in xe2x80x9cpage modexe2x80x9d, i.e., for each block having a fixed size and called xe2x80x9ca pagexe2x80x9d, is employed for reducing the cycle time in memory access, i.e., the time interval between a memory access and next memory access, to achieve high-speed input/output of data to/from the memory. In this case, it is important for efficiency to frequently use the page mode when inputting/outputting data to/from the DRAM.
In a prior art decoder performing decoding with error correction, input data, which have been coded and are to be subjected to error correction, are temporarily stored in a buffer. As this buffer, an FIFO buffer according to FIFO (first-in first-out) is used. Then, the data stored in the FIFO buffer are fetched to be stored in a DRAM in a form suitable for an error correction array which is a format for error correction. Thereafter, the data stored in the DRAM are fetched to be subjected to ECC.
For example, in the case of using an error correction format having parity data in the column direction, when the data to be subjected to ECC are stored in the paging DRAM, the data are stored in the column direction according to the column-direction addresses of the DRAM. This storage enables data reading using the page mode in the column direction when the data stored in the DRAM are read for ECC, whereby high-speed memory access is achieved.
Also in a prior art encoder performing coding with error correction, similar processing is carried out. In the encoder, input data to be subjected to coding and error correction are temporarily stored in a buffer, and the data stored in the buffer are fetched to be stored in a DRAM in a form suitable for an error correction array which is a format for error correction. Then, the data so stored are subjected to coding with error correction, thereby generating coded data to which parity data for error correction are added.
For example, in the case of using an error correction format having parity data in the column direction, when the data to be subjected to ECC are stored in the paging DRAM, the data are stored in the column direction in accordance with the column-direction addresses of the DRAM. This storage enables data reading using the page mode in the column direction when the data stored in the DRAM are read for ECC coding, whereby high-speed memory access is achieved.
Further, in the prior art decoder, interpolation is carried out in the FIFO buffer to deal with the case where defects occur in the input data. For example, when using data sync bytes which are inserted in the input data at intervals of a predetermined amount of data, the data sync bytes are detected to check the amount of data between the data sync bytes included in the data stored in the FIFO buffer, and when the amount of data is less than a predetermined amount, dummy data is added to make the data between the data sync bytes have the predetermined amount.
In recent years, in order to improve the ECC precision, an error correction array of product codes, which is a format for assigning error correction codes to both rows and columns, has been used more frequently. When using this format, it is necessary to perform syndrome operation (polynomial operation) for both the row direction and the column direction in ECC, and the burden on the operation is considerable.
Furthermore, when performing error correction in a decoding process in a system having a control processor such as a computer system, this operation is repeated three times in the routine of xe2x80x9crow-directionxe2x86x92column-directionxe2x86x92row-directionxe2x80x9d or xe2x80x9ccolumn-directionxe2x86x92row directionxe2x86x92column directionxe2x80x9d, to improve reliability of error correction. In this case, due to the increase in the frequency of access to the DRAM storing the data to be processed, high-speed access in the row direction (or the column direction) is required when the operation is carried out in the order of row-directionxe2x86x92column-directionxe2x86x92row-direction (or column-directionxe2x86x92row directionxe2x86x92column direction).
Moreover, when performing data processing in a computer system or the like, it is desirable to minimize the period during which a processor like a host CPU occupies a bus. Therefore, in a drive unit performing recording/reproduction of data in/from a data recording medium such as an optical disk, it is increasingly needed to increase the recording/reproduction speed, or the data transfer speed between the drive unit and a control unit such as a host computer. In such system, it is also desired to increase the error correction speed.
Consequently, in the data processing in this system, high-speed data input/output are strongly desired and, when using a paging DRAM, it is required that the page mode is used more frequently in both the row direction and the column direction to reduce the frequency of access to the DRAM.
In the prior art encoder or decoder, however, since the data stored in the FIFO buffer are fetched to be stored in the DRAM in the order as entered to the buffer, if the data are stored by using the page mode more frequently for one of the row direction and the column direction, the page mode cannot be frequently used for the other direction.
For example, in the case where the data have been sequentially input in the column direction of the correction array and then sequentially stored in the column direction of the DRAM, when the data are read in the column direction of the array to be subjected to error correction, the data can be successively read using the page mode. However, when the data are read in the row direction of the array, since the possibility that successive data are present in the same row is not very high, the page mode cannot be used frequently.
In the above-described ECC included in the decoding process, when the stored data are fetched in the order of row-directionxe2x86x92column-directionxe2x86x92row-direction and subjected to ECC, delays in the row-direction reading which has more access cycles than the column-direction reading are considerable, resulting in a reduction in efficiency in the whole reading process. Consequently, efficiency in the whole ECC is reduced. This means that the paging DRAM is not efficiently utilized, resulting in that the device resources are not efficiently utilized.
Furthermore, in the case of coding, data are usually processed from row-direction to column-direction or from column direction to row direction. Also in this case, processing efficiency is not satisfactorily high in one of these directions, as described above. Especially when the drive unit is able to perform high-speed recording, this ability of high-speed recording is not sufficiently utilized when rapid error correction is not performed.
Moreover, in the prior art decoder, as described above, the amount of input data is checked when the data are stored in the FIFO buffer and, if the amount is not sufficient, dummy data for interpolation is generated and inserted into the data in the FIFO buffer. So, if the FIFO buffer does not have a sufficient capacity, there is a possibility that the storage is not carried out smoothly due to delays caused by the interpolation, resulting in data defects. On the other hand, to use a large-capacity FIFO buffer to avoid such risk results in increased circuit scale and increased cost.
Further, when recording or transmitting digital data, interleaving (rearrangement of data according to a specific rule) is carried out to facilitate the countermeasure against the case where continuous data defects occur due to, for example, a flaw in the recording medium. For the data which has been subjected to interleaving in the encoder, deinterleaving which is the inverse of interleaving is required in the decoder.
In the prior art decoder, when data storage is performed with priority to the column direction, the interleaving cannot be released in the row direction while it can be released in the column direction, whereby the data which have not been deinterleaved in the row direction are stored in the DRAM. Accordingly, when the data so stored in the DRAM are subjected to ECC in the subsequent stage, deinterleaving in the row direction is also required, and thus the burden on the ECC becomes considerable.
Moreover, in the prior art encoder, since interleaved coded data cannot be obtained, it is necessary to perform interleaving in the subsequent process such as sync signal addition or modulation and, therefore, the burden on the subsequent process is increased.
The present invention is made to solve the above-described problems and has for its object to provide a data transfer device which stores data to be subjected to ECC into a paging DRAM when performing ECC according to an error correction array of product codes in a coding or decoding process and, more specifically, a data transfer device which can frequently use the page mode for both the process in the row direction and the process in the column direction, and thereby utilize the device resources efficiently to improve efficiency in the process.
It is another object of the present invention to provide a data transfer device which realizes, when storing data in a RAM, the data storage state equivalent to the state where interpolation for data defects has been performed, to make interpolation in the previous-stage FIFO buffer unnecessary, i.e., a data transfer device which can deal with data defects without increasing the capacity of the FIFO buffer.
It is still another object of the present invention to provide a data transfer device which stores data to be subjected to ECC in a RAM, with a format which has been subjected to interleaving or deinterleaving, to reduce the burden on the subsequent process.
It is yet another object of the present invention to provide a data transfer method for storing data to be subjected to ECC into a paging DRAM when performing ECC according to an error correction array of product codes in a coding or decoding process and, more specifically, a data transfer method which can frequently use the page mode for both the process in the row direction and the process in the column direction to improve efficiency in the process.
It is a further object of the present invention to provide a data transfer method which realizes, when storing data in a RAM, the data storage state equivalent to the state where interpolation for data defects has been performed, to make interpolation in the previous-stage FIFO buffer unnecessary, i.e., a data transfer method which can deal with data defects without increasing the capacity of the FIFO buffer.
It is a still further object of the present invention to provide a data transfer method for storing data to be subjected to ECC into a RAM, with a format which has been subjected to interleaving or deinterleaving, to reduce the burden on the subsequent process.
According to a first aspect of the present invention, there is provided a data transfer device for successively storing data in data storage means or successively reading data from the data storage means in data processing using an array of m rowsxc3x97n columns, and the device comprises: data storage means for retaining data which have been stored in storage positions specified by row addresses indicating the positions in the row direction and column addresses indicating the positions in the column direction; transfer address generation means for generating transfer addresses comprising the row addresses and the column addresses so that the storage positions for transferred data are successively specified in each of storage blocks having a predetermined size and arranged in the row direction of the data storage means; and transfer control means for controlling data transfer to the data storage means by using the transfer addresses generated by the transfer address generation means.
According to a second aspect of the present invention, in the above-described data transfer device, the transfer address generation means comprises: base-n count means for counting the successively-transferred data according to the base-n notation; base-i count means for counting carries generated in the counting process of the base-n count means, according to the base-i notation, with the number of the storage blocks in the column direction being i; column address offset value generation means for generating column address offset values indicating origins in the column direction of the respective storage blocks, according to the result from the base-i count means; base-k count means for counting the input data according to the base-k notation, with the size of each storage block in the column direction being k, thereby generating reference column address values indicating storage positions in the column direction within the respective storage blocks; base-n/k count means for counting carries generated in the counting process of the base-k count means according to the base-n/k notation, thereby generating reference row address values indicating storage positions in the row direction within the respective storage blocks; base-m/i count means for counting carries generated in the counting process of the base-i count means according to the base-m/i notation; row address offset value generation means for generating row address offset values indicating origins in the row direction of the respective storage blocks, according to the result of the count by the base-m/i count means; column address generation means for generating the column addresses by using the column address offset values and the reference column address values; and row address generation means for generating the row addresses by using the row address offset values and the reference row address values.
According to a third aspect of the present invention, in the above-described data transfer device, the successively-transferred data include data synchronous signals which can be specified by a format, at intervals of a predetermined amount of the data; and the device further including count instruction means for obtaining the storage positions for data which follow the data synchronous signal by arithmetic operation, according to the data synchronous signal, and controlling the transfer address generation means to generate transfer addresses indicating the storage positions so obtained.
According to a fourth aspect of the present invention, the above-described data transfer device further includes: base-n count means for counting the successively-transferred data according to the base-n notation; base-m count means for counting carries generated in the base-n count means according to the base-m notation; and count instruction means for obtaining storage positions of specific data by arithmetic operation and controlling the transfer address generation means to generate transfer addresses indicating the obtained storage positions, when transferring the result of predetermined rearrangement performed to the specific data among the transferred data according to the result from the base-m count means.
According to a fifth aspect of the present invention, in the above-described data transfer device, the data processing using an array of m rowsxc3x97n columns comprises data processing using an array of m1 rowsxc3x97n1 columns and data processing using an array of m2 rowsxc3x97n2 columns, on condition that m1 greater than m2 and n1 greater than n2.
According to a sixth aspect of the present invention, the above-described data transfer device further includes: error correction data conversion means performing predetermined data conversion with error correction to the data stored in the data storage means; and conversion address generation means for specifying storage positions for data to be read from the data storage means for the data conversion.
According to a seventh aspect of the present invention, the above-described data transfer device further includes: data format conversion means performing signal conversion between a data format processed by the data transfer device and a data format in a recording medium for data storage; and data transfer means for data storage, performing data transfer between the data transfer device and the recording medium.
According to an eighth aspect of the present invention, thee is provided as data transfer method for successively storing data in data storage means for successively reading data from the data storage means in data processing using an array of m rowsxc3x97n columns, while specifying the storage positions by row addresses indicating the positions in the row direction and column addresses indicating the positions in the column direction, and this method comprises: transfer address generation step of generating transfer addresses comprising the row addresses and the column addresses so that the storage positions for the transferred data are successively specified in each of storage blocks having a predetermined size and arranged in the row direction of the data storage means; and transfer control step of controlling data transfer to the data storage means by using the transfer addresses generated in the transfer address generation step.
According to a ninth aspect of the present invention, in the above-described data transfer method, the transferred data have data synchronous signals which can be specified by a format, at intervals of a predetermined amount of the data; and the method further includes count instruction step of obtaining the storage positions for data which follow the data synchronous signal, by arithmetic operation, according to the data synchronous signal, and controlling the transfer address generation means to generate transfer addresses indicating the storage positions so obtained.
According to a tenth aspect of the present invention, the above-described data transfer method further includes: base-n count step of counting the successively-transferred data according to the base-n rotation; base-m count step of counting carries generated in the base-n count step according to the base-m notation; and count instruction step of obtaining storage positions for specific data by arithmetic operation and controlling the process in the transfer address generation step to generate transfer addresses indicating the obtained storage positions, when transferring the result of predetermined rearrangement performed to the specific data among the transferred data according to the result from the base-m count step.
According to an eleventh aspect of the present invention, in the above-described data transfer method, the data processing using an array of m rowsxc3x97n columns comprises data processing using an array of m1 rowsxc3x97n1 columns and data processing using an array of m2 rowsxc3x97n2 columns, on condition that m1 greater than m2 and n1 greater than n2.
According to the twelfth aspect of the present invention, in the above-described data transfer method, the array of m1 rowsxc3x97n1 columns comprises a main data part corresponding to the array of m2 rowsxc3x97n2 columns, and an error correction parity part which is generated by a predetermined method based on the main data part.
According to a thirteenth aspect of the present invention, the above-described data transfer method further includes error correction data conversion step of performing predetermined data conversion with error correction to the data stored in the data storage means; and conversion address generation step of specifying storage positions for data to be read from the data storage means for the data conversion.
According to a fourteenth aspect of the present invention, in the above-described data transfer method, the error correction data conversion step is error correction data coding step of performing a predetermined data coding process including error correction; and the conversion address generation step is coding address generation step of specifying storage positions for data to be read for the data coding process.
According to a fifteenth aspect of the present invention, in the above-described data transfer method, the error correction data conversion step is error correction data decoding step of performing a predetermined data decoding process including error correction; and the conversion address generation step is decoding address generation step of specifying storage positions for data to be read for the data decoding process.
According to a sixteenth aspect of the present invention, the above-described data transfer method further includes: data format conversion step of performing signal conversion between a data format used in the data transfer method and a data format in a recording medium for data storage; and data transfer step for data storage, performing data transfer to the recording medium.
According to a seventeenth aspect of the present invention, in the above-described data transfer method, the data format conversion step is data modulation step of performing modulation to coded data generated in the data coding process; and the data transfer step is data recording step of recording the data in the recording medium.
According to an eighteenth aspect of the present invention, in the above-described data transfer method, the data format conversion step is data demodulation step of performing demodulation to generate coded data to be processed in a data decoding process; and the data transfer step is data reproduction step of reading demodulated data from the recording medium.